1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, relates to a liquid crystal display device and a fabrication method thereof that provide improved electrical contact characteristics for mounting a driving integrated circuit (IC) thereon.
2. Discussion of the Related Art
Recently, as interests in information displays are growing and the demand for portable information devices, e.g., a mobile phone, is increasing, researches and commercialization of lightweight compact flat panel display (FPD) devices are actively ongoing. Among FPD devices, a liquid crystal display device, which employs optical anisotropy of liquid crystal molecules, exhibits excellent resolution and color quality, and has been widely used in small electronic devices, such as mobile terminals, and notebook computers. In general, an LCD device employed for small electronic devices has a different structure from an LCD for a large-scale LCD device.
FIG. 1 is a plan view illustrating an LCD device according to the related art. In FIG. 1, an LCD device includes a substrate 12. The substrate 12 includes an image display region 10 having a plurality of pixels P, a plurality of gate link lines GL1 . . . GLm and a plurality of data link lines 30. Although not shown, a plurality of data lines are arranged in a vertical direction and a plurality of gate lines are arranged in a horizontal direction in the image display region 10. The gate lines and the data lines intersect each other to define the pixels P. The gate lines of the image display region 10 are respectively connected with the gate link lines GL1 . . . GLm, and the data lines are respectively connected with the data link lines 30.
In addition, a driving integrated circuit (IC) 20 is mounted outside the display region 10 and along an edge of the substrate 12. The driving IC 20 applies data signals and scan signals to the pixels P through the gate link lines GL1 . . . GLm and the data link lines 30. Since the LCD device is employed in a small-size electronic device, to maximize the surface area of the image display region 10, regions other than the image display region 10 become narrow or small. Accordingly, a gate driving unit and a data driving unit, which are individually provided in a medium or large LCD device, are formed as a single integrated circuit in a small LCD device.
For example, the driving IC 20 includes a gate driving unit and a data driving unit. In particular, the driving IC 20 includes a plurality of output ports for outputting scan signals and a plurality of output ports for outputting data signals. The output ports for outputting data signals typically are positioned at the central portion, and the output ports for outputting scan signals are positioned at side portions.
Thus, the data link lines 30 electrically connect to the output ports at the central portion of the driving IC 20, and the gate link lines GL1 . . . GLm electrically connect to the output ports at side portions of the driving IC 20. In particular, a first half of the gate link lines GL1 . . . GLm are on a left side portion and a second half of the gate link lines GL1 . . . GLm are on a right side portion. In addition, the first half of the gate link lines GL1 . . . GLm are connected to gate lines located at a upper region of the image display region 10, and the second half of the gate link lines are connected to gate lines located at a lower region of the image display region 10.
A plurality of conductive bumps functioning as terminals for allowing the gate link lines GL1 . . . GLm and the data link lines 30 to electrically contact the driving IC 20 are formed on the substrate 12. Since the output ports for outputting the scan signals and the data signals are in a row in the driving IC 20, the bumps also are disposed in a row.
FIG. 2 is a plan view illustrating connections between a substrate and a driving IC according to the related art, and FIG. 3 is a cross-sectional view along I-I in FIG. 2. In FIG. 2, a plurality of input bumps 140 and a plurality of output bumps 150 are formed on a region of the substrate where the driving IC 120 is mounted. Control signals and data signals are applied to the input bumps 140 from a timing controller of the LCD device, and scan signals and data signals are outputted through the output bumps 150. The output bumps 150 include gate output bumps 151a and 151b for outputting scan signals and data output bumps 152 for outputting data signals. A plurality of input/output terminals are provided on a rear surface of the driving IC 120 electrically connected to the gate output bumps 151a and 151b and the data output bumps 152.
The gate link lines and the data link lines arranged on the substrate are formed simultaneously when a pattern of a liquid crystal display panel is formed on a mother substrate. In particular, the gate link lines are formed simultaneously when the gate lines are formed in every liquid crystal display panel, and the data link lines are formed when the data lines are formed in every liquid crystal display panel. Thus, since the gate link lines and the data link lines are each formed on a different layer, a step height of the gate output bumps 151a and 151b and a step height the data output bumps 152 are different.
As shown in FIG. 3, the liquid crystal display panel includes gate link lines 235 formed on a substrate 212, a gate insulation layer 231 formed on the entire surface of the substrate 212 including the gate link lines 235, and a passivation layer 234 formed on the entire surface of the substrate 212 including data link lines 230 and gate link lines 235. In addition, data bumps 252 are disposed at contact holes 237 formed in the passivation layer 234 and electrically contact the data link lines 230. Gate bumps 251 are disposed at the contact holes 239 formed in the passivation layer 234 and the gate insulation layer 231 and electrically contact the gate link lines 235.
The driving IC 220 is mounted on the substrate 212, and a plurality of input/output terminals 221 are on a rear or lower surface of the driving IC 220. The terminals 221 are electrically connected to the gate bumps 251 and the data bumps 252 through conductive balls 238.
Further, the gate link lines 235 and the data link lines 230 are formed in different layers. In particular, the gate link lines 235 are formed simultaneously when the gate lines are formed on the substrate 212. On the other hand, the data link lines 235 are formed simultaneously when the data lines, drain electrodes and source electrodes are formed on the substrate 212 during a process of forming thin film transistors (TFTs). Accordingly, an active layer 232 is formed between the data link line 230 and the gate insulation layer 231.
Since the data link lines 230 and the gate link lines 235 are in different layers, a step or vertical topographic offset occurs. A step also occurs between the data bumps 252 formed on the data link lines 230 and the gate bumps 251 formed on the gate link lines 235. As a result, the distance d1 between the gate bumps 251 and the input/output terminals 221 and the distance d2 between the data bumps 252 and the input/output terminals 221 are different from each other. More specifically, the distance d1 is greater than the distance d2.
Further, the conductive balls 238 are pressed between the data bumps 252 and the input/output terminals 221 due to the distance d2, but the conductive balls 238 located between the gate bumps 251 and the input/output terminals 221 are not pressed due to the distance d1. Thus, a contact deficiency occurs the between gate bumps 251 and the input/output terminals 221, thereby reducing contact efficiency between the driving IC 220 and the substrate 212. Such contact deficiency interferes with transferring control signals and data signals from the timing controller to the driving IC. Such contact deficiency also interferes with transferring scan signals and data signals from the driving IC to the gate link lines and the data link lines, thereby causing the LCD device to be driven erroneously.